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A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices

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3 Author(s)
Dai Zhang ; Dept. of Electr. Eng., Linkoping Univ., Linköping, Sweden ; Bhide, A. ; Alvandpour, A.

This paper describes an ultra-low-power SAR ADC in 0.13-μm CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-μm CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.

Published in:

ESSCIRC (ESSCIRC), 2011 Proceedings of the

Date of Conference:

12-16 Sept. 2011

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