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A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS

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4 Author(s)
Nguyen, R. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA ; Raynaud, C. ; Cathelin, A. ; Murmann, B.

A 6.7-ENOB, 500-MS/s pipeline ADC is realized using low-power charge pump-like dynamic gain stages operating with incomplete transient settling. The experimental converter occupies an active area of 0.02 mm2 in 65-nm SOI CMOS and dissipates 5.1 mW from a 1.2-V supply. It achieves an SNDR of 41.5 dB for inputs near Nyquist, corresponding to a figure of merit of 98 fJ/conv.-step.

Published in:

ESSCIRC (ESSCIRC), 2011 Proceedings of the

Date of Conference:

12-16 Sept. 2011

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