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A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS

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7 Author(s)
Agarwal, A. ; Circuits Res. Lab., Intel Corp., Hillsboro, OR, USA ; Hsu, S. ; Mathew, S. ; Anders, M.
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A 128-entry × 128b content addressable memory (CAM) design enables 145ps search operation in 1.0V, 32nm high-k metal-gate CMOS technology. A high-speed 16b wide dynamic AND match-line, combined with a fully static search-line and swapped XOR CAM cell simulations show a 49% reduction of search energy at iso-search delay of 145ps over an optimized high-performance conventional NOR-type CAM design, enabling 1.07fJ/bit/search operation. Scaling the supply voltage of the proposed CAM enables 0.3fJ/bit/search with 1.07ns search delay at 0.5V.

Published in:

ESSCIRC (ESSCIRC), 2011 Proceedings of the

Date of Conference:

12-16 Sept. 2011

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