By Topic

FPGA-Based Acceleration of Block Matching Motion Estimation Techniques

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Gonzalez, D. ; Comput. Archit. Dept., Complutense Univ. of Madrid, Madrid, Spain ; Botella, G. ; Mokheerje, S. ; Meyer-Base, U.

This paper focuses on the hardware acceleration of Block Matching motion estimation techniques (Search reduction family) suitable for the standard H.264/AVC MPEG-4 part 10 video compression. Many representative motion estimation search algorithms are explained here. As hardware, the well known Altera DE2 platform with a Cyclone II EP2C35F672C6 is used with a soft core NIOS II processor. C2H compiler which permits us to speed up the system at least two magnitude order is used to accelerate our source code. The paper shows the results in terms of performance and resources needed. This is the starting point to accelerate motion estimation algorithms using many strategies considering an ad-hoc motion estimation processor.

Published in:

Field Programmable Logic and Applications (FPL), 2011 International Conference on

Date of Conference:

5-7 Sept. 2011