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The dynamic partial reconfiguration of FPGAs is a method which modifies parts of FPGA configuration memory at run-time. The hardware resources and time overhead needed to perform a partial reconfiguration (PR) can significantly impact overall system cost and performance and must be considered early in the design cycle. Unfortunately, predicting reconfiguration overhead is difficult especially in the presence of non-deterministic factors such as the sharing of resources with traffic not related to the PR process. Thus, current design practices include the measurement of overhead but only after the system has been built thus limiting the number of candidates that can be evaluated. We propose a flexible approach for modeling the PR datapath based on Queueing Theory such that we can estimate performance trends and bottlenecks of the PR process while considering the impact of shared resources. Performance trends are provided for an example system to demonstrate the effectiveness of the approach.