Skip to Main Content
Clock jitter degrades the performance of data converters in mixed-signal systems. The sampling operation inherent to analog-to-digital and digital-to-analog (D/A) conversion is inevitably subject to random timing uncertainties. These small timing errors introduce a noise component into the system that degrades the effective resolution of the data converters. Although the effect of sampling jitter on single sine waves is well understood, this classical result cannot be generalized to multitone signals, which are nowadays widely used as information carriers in digital communication systems. In this brief, an approximation for the phase noise of integrated clock sources is used to derive an analytical expression for the jitter noise power spectral density (PSD) of unmodulated multitone signals at the output of an ideal sampler. This result requires only a minimum number of basic system parameters for a quick and accurate estimation of the needed sampling clock quality for data converters used in multicarrier processing. In addition to behavioral simulation, the obtained expression is verified experimentally using a CMOS D/A converter with intentionally jittered sampling clock.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:58 , Issue: 10 )
Date of Publication: Oct. 2011