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A Continuous-Time Sigma-Delta (ΣΔ) Modulator for Bluetooth with 52MHz sampling frequency in a 1.2V 65nm CMOS process is presented. The modulator has a proposed single-stage 3rd-order 4-bit architecture, which employs a dual-loop feedback method to compensate the loop delay up to one clock period. A 4-bit flash ADC and a 4-bit current-steering DAC are used to improve the resolution and stability. Non-Return-Zero (NRZ) pulse shape of feedback-DAC is adopted to alleviate jitter sensitivity. Feedforward gains of the loop filter are realized by capacitors ratios. This approach can reduce the power consumption and provide better linearity. The basic data-weighted-averaging (DWA) digital linearization circuit is used to compensate the DAC mismatch errors efficiently. The co-simulation result at circuit level can achieve 80dB DR within 1MHz signal bandwidth without clock jitter or device noise.