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A novel topology for a high speed voltage level shifter (VLS) is presented. It features a built-in short circuit current reduction which increases the speed and reduces the power consumption. Unlike the conventional VLSs, the proposed VLS does not need complex digital timing signals. The simplicity of its operation results into robustness of operation, high speed and low power. The VLS was designed in CMOS 0.18um process. Simulation results, at the layout extraction level, are presented to validate the design concept. The speed and energy consumption of the VLS are compared with the state of the art VLSs. The proposed VLS proves to be better in both the speed and power aspects than the state of the art VLSs.
Date of Conference: 29-31 Aug. 2011