By Topic

A Method to Generate Verification Condition Generator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zhaopeng Li ; Sch. of Comput. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China ; Yang Zhang ; Yiyun Chen

We propose a method to generate certain verification condition generators (VCGens, for short) automatically to be used in certifying compilers or other verification tools in this paper, to alleviate the burden of developing various kinds of VCGens in the domain-specific program verification tools. We introduce a new methodology for describing the rules in the verification condition calculation. We have implemented a prototype of VCGEN2(VCGenGen) using C++. This tool provides a series of interfaces named action functions to the users. Users can describe the calculation rules by combining these action functions. And our tool also embeds a parser generator, so users need to feed in the grammar of the languages along with the calculation rules. If there is no error, VCGEN2 outputs the corresponding VCGen with respect to the user-defined languages and rules. We have used our prototype to generate a number of VCGens successfully as demonstration.

Published in:

Theoretical Aspects of Software Engineering (TASE), 2011 Fifth International Symposium on

Date of Conference:

29-31 Aug. 2011