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Proposal of instruction level modeling for Dynamically Reconfigurable Processor using SystemC

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1 Author(s)
Junji Kitamichi ; Graduate School of Computer Science and Engineering, The University of Aizu, Tsuruga, Ikki-machi, Aizu-Wakamatsu, Fukushima 965-8580, JAPAN

Recently, various kinds of Dynamically Reconfigurable Processors (DRPs) have been proposed. In this paper, we describe a modeling method of a DRP using a Dynamic Module Library (DML), which we have developed for the modeling of general-purpose dynamically reconfigurable architectures at the system design level. The DML is an extended SystemC library and enables the modeling of the dynamic generation and elimination of modules, ports and channels and the dynamic connection and dispatch between port and channel. Using the DML, we can model the DRP naturally at the abstract level, where the instruction set architecture and the structure specification of DRP are decided. The proposed processor consists of a core part, dynamically reconfigurable operation units and a controller for them, and we describe the modeling method of them.

Published in:

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

Date of Conference:

12-14 Oct. 2009