GenerateRCS: A high-level design tool for generating reconfigurable computing systems

The traditional design flow for run-time reconfigurable hardware systems is very time-consuming until today. There exist some tools alleviating the generation of reconfigurable systems, but none of them provides a seamless high-level design flow decreasing the threshold of acceptance for the non-specialist in reconfigurable hardware. Most of these tools focus on the placement of the reconfigurable modules and their interfaces as well as on the generation of the partial bitstreams, but none of them focus on the required high-level transformations, such as for example the automatic instantiation of communication interfaces in the HDL-file. In this paper a tool called GenerateRCS is presented, which provides a graphical user interface (GUI) for an easy system integration on reconfigurable hardware. Furthermore, it can be used to graphically view the components, signals and parameters of a VHDL-file. GenerateRCS can be integrated into high-level tools such as Xilinx Embedded Development Kit (EDK). This way, reconfigurable computing systems can be generated very fast and without the need to write HDL -code.