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Performance and energy evaluation of memory hierarchies in NoC-based MPSoCs under latency

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3 Author(s)
Girao, G. ; Inst. of Inf., Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil ; Barcelos, D. ; Wagner, F.R.

This paper presents a performance evaluation study on distinct memory hierarchies considering an NoC-based MPSoC environment. This evaluation considers two sets of experiments. The first one evaluates the performance and energy efficiency of four different memory hierarchies in a situation with no external traffic. In the second experiment, a traffic generator is responsible for the injection of synthetic traffic into the system, in order to increase the latency of the NoC and evaluate the performance of each memory model in this situation. Results show that, with no external traffic, the distributed memory presents better results for applications with low amount of data to be transferred. On the other hand, results suggest that shared and distributed shared memories present the best results for applications with high data transferring needs. In the second experiment, with external traffic, for applications with low communication bandwidth requirements, a memory organization that is physically centralized and logically shared is shown to have a smooth performance degradation when external traffic rises up to 20% of network capacity (22% decrease for an application demanding high communication, and 34% decrease for a low communication one). In contrast, a distributed memory model presents 2% of degradation in an application with high communication requirements, when traffic rises up to 20% of network capacity, and reaches 19% of degradation in low communication ones. Shared and distributed shared memory models are shown to present lower tolerance to high latencies.

Published in:

Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on

Date of Conference:

12-14 Oct. 2009