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A comprehensive submicrometer MOST delay model and its application to CMOS buffers

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3 Author(s)
P. Cocchini ; Dept. of Electron., Politecnico di Torino, Italy ; G. Piccinini ; M. Zamboni

In this paper, an accurate delay model for MOS transistors in submicrometer CMOS digital circuits is presented. It takes into account a ramp shape input voltage and a feedforward capacitive coupling between gate and drain nodes, along with the main second-order effects present in short-channel MOS transistors. The proposed model shows an average agreement with SPICE simulations of 3% in the calculation of the propagation time, tested on a minimum inverter with a 0.7-μm CMOS reference technology for a wide range of input voltage slopes. An example of application in optimization algorithms regarding CMOS tapered buffers is also reported. A maximum error ranging from 3-6% with respect to SPICE has been found for the optimized circuits

Published in:

IEEE Journal of Solid-State Circuits  (Volume:32 ,  Issue: 8 )