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Supply and threshold voltage scaling for low power CMOS

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3 Author(s)
Gonzalez, R. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Gordon, B.M. ; Horowitz, M.A.

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 8 )