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A 6.25Gb/s Decision Feedback Equalizer in 0.18??im CMOS Technology for High-Speed SerDes

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2 Author(s)
Zhuangjing Feng ; Inst. of RF& OE-ICs, Southeast Univ., Nanjing, China ; Qingsheng Hu

In this paper a 6.25Gb/s two-tap half-rate decision feedback equalizer (DFE) is designed and implemented in TSMC 0.18μm CMOS technology. After system-level simulation based on Simulink and pre-simulation, the DFE architecture is designed and corresponding parameters are determined. To achieve high data rate, CML DFFs, summers and multiplex are all designed elaborately. The total area including I/O pads is 0.3×0.5μm2. Post simulation results show that the horizontal eye opening of recovered data is 0.7 UI at 6.25Gb/s.

Published in:

Wireless Communications, Networking and Mobile Computing (WiCOM), 2011 7th International Conference on

Date of Conference:

23-25 Sept. 2011