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To improving the efficiency of test pattern generation for combinational circuits based on the Boolean satisfiability (SAT) method, a TRL-based (Total Reconvergence Line) BDD (binary decision diagram) learning heuristics is presented in this paper. This heuristics combine the respective strengths of BDD, SAT and circuit structure based methods to solve local signal correlations. It firstly makes an analysis of the circuit topological structure to gather the information about local signal correlation through BDD learning. The above learned information in the conjunctive normal form clauses is then used to restrict and focus the overall search space of SAT-based test pattern generation. The experimental results show the validity of this approach.