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This contribution presents some results in the design and implementation of an universal functional test generator for VLSI circuits, such as microprocessor and processor cores. Our approach to test generation - the functional test generation method - is based on knowledges of instruction set architecture (ISA), functional description of VLSI systems at functional VHDL level and promising concept of software-based self test (SBST), for better test generation the genetic algorithm (GA) properties based on evolutionary strategiesw are used. The algorithm for automatic generation of test (normal executable test sequence of instructions) and arrangement, is used in very flexible and effective tool - Automatic Functional Test Generator (AFTG). The determination of the test efficiency of instruction testing mixes is discussed.