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On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks

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4 Author(s)
Alessandro Barenghi ; Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy ; Guido Bertoni ; Fabrizio De Santis ; Filippo Melzani

Side-channel attacks are a realistic threat to the security of real world implementations of cryptographic algorithms. In order to evaluate the resistance of designs against power analysis attacks, power values obtained from circuit simulations in early design phases offer two distinct advantages: First, they offer fast feedback loops to designers, second the number of redesigns can be reduced. This work investigates the accuracy of design time power estimation tools in assessing the security level of a device against differential power attacks.

Published in:

Digital System Design (DSD), 2011 14th Euromicro Conference on

Date of Conference:

Aug. 31 2011-Sept. 2 2011