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Double-gate FinFETs have proved to be a promising alternative for deep sub-micron bulk CMOS. In this paper, we have investigated the feasibility of FinFET transistors in asynchronous design which has gained much attention for its advantages such as absence of clock distribution, process variation aware performance, and robustness. Excellent short-channel characteristic, low leakage power, threshold voltage control and the potential of designing area-efficient circuits are the motivation to employ FinFET transistor in asynchronous circuit design. We have designed three novel FinFET-based asynchronous static C-elements which differ in front gate and back gate connections. They are evaluated in terms of leakage and dynamic power, area, and delay characteristics and compared against bulk CMOS C-element in 32nm technology. With technology scaling, vulnerability of combinational logic to soft errors exponentially increases. In this paper we also examine these C-elements nodes sensitivity against soft errors and propose a robust logic. We show that our proposed robustness method increases robustness of the most sensitive node in Shorted gate (SG) and Low power (LP) C-elements 60 times. A dual rail Muller pipeline has been designed with each kind to evaluate our C-elements and compare them to bulk MOSFET pipeline. Compared to SG, simulation results show that Independent gate (IG) and LP modes are most efficient in area and leakage power respectively and in terms of robustness SG and LP modes show better robustness than IG mode.
Date of Conference: Aug. 31 2011-Sept. 2 2011