By Topic

On Failure Rate Assessment Using an Executable Model of the System

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Neishaburi, M.H. ; Dept. of Electr. Eng., McGill Univ., Montreal, QC, Canada ; Zilic, Z.

Statistical data from many application fields confirm that SoC products implemented in modern deep submicron technologies are getting more and more susceptible to transient errors. Although thorough and comprehensive understanding of the services that SoCs provide is the key to systematic development, designers no longer can ignore the emerging reliability issues. In fact, proper actions should be carried out at various stage of production to mitigate the effect of transient errors. Having failure rate of a system at early stage of SoC development will help companies and designers to make right decisions at right time concerning the usage of error protection mechanisms with suitable intensity across different modules. This paper proposes a new method to estimate failure rate of modules inside a SoC.

Published in:

Digital System Design (DSD), 2011 14th Euromicro Conference on

Date of Conference:

Aug. 31 2011-Sept. 2 2011