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Statistical data from many application fields confirm that SoC products implemented in modern deep submicron technologies are getting more and more susceptible to transient errors. Although thorough and comprehensive understanding of the services that SoCs provide is the key to systematic development, designers no longer can ignore the emerging reliability issues. In fact, proper actions should be carried out at various stage of production to mitigate the effect of transient errors. Having failure rate of a system at early stage of SoC development will help companies and designers to make right decisions at right time concerning the usage of error protection mechanisms with suitable intensity across different modules. This paper proposes a new method to estimate failure rate of modules inside a SoC.