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With technology scaling down, leakage power plays an increasingly important role in low power logic design and becomes more susceptible to process and temperature fluctuations. In this paper, a novel adaptive body bias technique is proposed to minimize leakage power and compensate process and temperature variations of nanoscale CMOS VLSI circuits in standby mode. Taking sub-threshold current, gate leakage and band-to-band current into consideration, the optimal value of body bias is determined by comparing the drain leakage currents of two off-state replica clusters applying two slight different body bias voltages. The proposed circuit was implemented using 90nm CMOS technology and applied on ISCAS85 benchmark circuits to validate its efficiency in different process corners (slow, typical and fast process) and operating temperatures (ranging from -40°C to 85°C). Simulation results indicate that the maximum standby leakage power reduction percentage is 93.94%. The proposed circuit can adaptively adjust the body bias to its optimal value during the whole standby period, which results in considerable reduction of leakage power and effective compensation of process and temperature variations.