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A 166MS/s 31mW pipelined interpolating ADC in 0.18µm CMOS with on-chip LDO regulator

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3 Author(s)
Li Jing-hu ; Sch. of Inf. Sci. & Eng., Harbin Inst. of Technol. (Weihai), Weihai, China ; Zhang Xing-bao ; Yu Ming-yan

In this paper, an 8-bit pipelined interpolating analog-to-digital converter (ADC) with on-chip LDO regulator is presented. The ADC incorporates a low voltage reference generator to generate high precision top and bottom reference voltage, a low noise LDO regulator to provide supply for the analog and digital module of the ADC, a low-voltage pipelined interpolating ADC to quantize the input analog signal. The LDO regulator decreases the supply voltage of the ADC and improves its power supply rejection. Simulation result shows the ADC achieves differential nonlinearity (DNL) of ±0.25LSB, integral nonlinearity (INL) of -0.25-0.5LSB, SNDR of 47dB at 166MHz sampling rate. The ADC is designed in SMIC 0.18μm mixed-signal CMOS process with operating supply range of 1.2-2.0V and power consumption of 31.2mW.

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Published in:

Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC), 2011  (Volume:2 )

Date of Conference:

26-30 July 2011