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A Laxity-Aware Memory Access Scheduler for High Performance Multimedia SoC

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4 Author(s)
Guangfei Zhang ; Res. Center of Microprocessor Technol., Chinese Acad. of Sci., Beijing, China ; Yifei Jiang ; Wenxiang Wang ; Menghao Su

Nowadays high-performance multimedia SoC design always integrates a variety of function units (FU) into a single chip and these FUs impose great stress on the shared memory system. To improve the memory system utilization and meet a wide range of bandwidth and latency requirements of these FUs, a well-designed memory scheduler that takes the quality-of-service (QoS) into account must be adopted. In this paper, a laxity-aware memory scheduler that can adaptively measure the laxity of each memory access task is proposed. Known the laxity of each memory access task, the proposed memory scheduler can guarantee the necessary bandwidth within a certain time interval, which is crucial to the performance and user experience of multimedia SoCs. Compared to previous proposed memory scheduling algorithms based on bandwidth allocating, the laxity-aware memory scheduler can obtain 14.5% decrease in memory access latency while preserving high DRAM data bus utilization.

Published in:

Computer and Information Technology (CIT), 2011 IEEE 11th International Conference on

Date of Conference:

Aug. 31 2011-Sept. 2 2011