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High-density interconnect board design for wafer-level packaging

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3 Author(s)
Wu, B. ; Intel Assembly & Test Technol. Dev., Folsom, CA, USA ; Brown, B. ; Warner, E.

The main advantage of wafer-level packaging is a smaller, thinner and lighter package with minimised electrical length and lower inductance. Presented is a printed circuit board electrical design to assemble a wafer-level package of a wireless radio core. The link impact and challenges are addressed in both time domain and frequency domain. The high-density interconnect substrate is analysed using a design of experiment technique to test the significance of structured variation. Its signal integrity and power delivery performance are compared with a similar design, but much thicker using a flip-chip package mounted on top of the conventional board. The thin board for wafer-level packaging provides better power delivery and signal performance than the traditional assembly.

Published in:

Electronics Letters  (Volume:47 ,  Issue: 20 )