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Workload-Aware Neuromorphic Design of the Power Controller

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4 Author(s)
Saurabh Sinha ; School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA ; Jounghyuk Suh ; Bertan Bakkaloglu ; Yu Cao

A workload-aware low-power neuromorphic controller for dynamic voltage and frequency scaling (DVFS) in very large scale integration (VLSI) systems is presented. The neuromorphic controller predicts future workload values and preemptively regulates supply voltage and frequency based on past workload profile. Our specific contributions include: 1) implementation of a digital and analog version of the controller in 45 nm CMOS technology, resulting in a 3% performance hit with a power overhead in the range of 10-150 μW from the controller circuit; 2) higher prediction accuracy compared to a software based OS-governed DVFS scheme, reducing wasted power and improving error margins; and 3) power savings of up to 52% and improvement of up to 15% compared to the OS-based scheme. The digital design has minimal power overhead and is more reconfigurable, while analog design is better suited for nonlinear and complex computational tasks.

Published in:

IEEE Journal on Emerging and Selected Topics in Circuits and Systems  (Volume:1 ,  Issue: 3 )