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Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower

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1 Author(s)
Blakiewicz, G. ; Dept. of Microelectron. Syst., Gdansk Univ. of Technol., Gdansk, Poland

An improved flipped voltage follower (FVF) and its application to a low-dropout (LDO) voltage regulator are presented. The proposed FVF improves most weaknesses of the classical one, namely its poor time response to the output current change from low to high value and poor stability for large capacitive load. The most important parameters of the modified FVF are analysed and described by analytical expressions. The parameters of the classical FVF and the improved one are compared and discussed. LDO regulator using the improved FVF is designed and implemented in AMS CMOS 0.35 m technology. The measurement results of a test circuit show its relatively high current efficiency of 74 and 99.93 for output current 100 μA and 50 mA, respectively. The output voltage overshoot and undershoot are below 46 and 75 mV for output current change from 0.1 to 50 mA with the rise and fall times equal to 0.3 s, and load capacitance 0 100 pF.

Published in:

Circuits, Devices & Systems, IET  (Volume:5 ,  Issue: 5 )