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A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

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9 Author(s)
Pilo, H. ; IBM Syst. & Technol. Group, Essex Junction, VT, USA ; Arsovski, I. ; Batson, K. ; Braceras, G.
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A 64 Mb SRAM macro has been fabricated in a 32 nm high-k metal-gate SOI technology. The SRAM features a 0.154 μm2 bit-cell, the smallest to date for a 32 nm SOI product. A 0.7 V VDDMIN operation is enabled by three assist features. Stability is improved by a bit-line regulation scheme which reduces charge injection into the bit-cell. Enhancements to the write path include an increase of 40% of bit-line boost voltage. Finally, a bit-cell-tracking delay circuit improves both performance and yield across the process space.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 1 )