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Browse Journals & Magazines > Electron Device Letters, IEEE ...> Volume:32 Issue:12 Help

Unusual C – V Characteristics of High-Resistivity SOI Wafers

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3 Author(s)
Nayak, P. ; Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA ; Seacrist, M. ; Schroder, D.K.

The maximum capacitance for bulk or Silicon on Insulator (SOI) wafers is governed by the gate/contact area. During our capacitance-voltage (C-V) characterization of high-resistivity SOI wafers with Al contacts directly on the Si film, we observed the maximum capacitance to be much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and buried oxide capacitance. In addition, an “S”-shape C-V plot was observed in the accumulation region.

Published in:
Electron Device Letters, IEEE  (Volume:32 ,  Issue: 12 )

Date of Publication: Dec. 2011

Page(s):
1659 - 1661
ISSN :
0741-3106
INSPEC Accession Number:
12376630
Digital Object Identifier :
10.1109/LED.2011.2167651
Product Type:
Journals & Magazines
Date of Publication :
03 October 2011
Date of Current Version :
21 November 2011
Issue Date :
Dec. 2011
Sponsored by :
IEEE Electron Devices Society

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