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The maximum capacitance for bulk or Silicon on Insulator (SOI) wafers is governed by the gate/contact area. During our capacitance-voltage (C-V) characterization of high-resistivity SOI wafers with Al contacts directly on the Si film, we observed the maximum capacitance to be much higher than that due to the contact area, suggesting bias spreading due to the distributed transmission line of the film resistance and buried oxide capacitance. In addition, an “S”-shape C-V plot was observed in the accumulation region.
Date of Publication: Dec. 2011