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Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis

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4 Author(s)
Anirban Sengupta ; Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada ; Reza Sedaghat ; Pallabi Sarkar ; Summit Sehgal

This paper presents a novel power efficient iterative Design Space Exploration (DSE) approach that finds the integrated solution to optimal/near-optimal scheduling and module selection with simultaneous reduction of the static power consumption of the design under the expenditure of minimal control steps. This iterative heuristic method is based on a novel priority function metric called 'Priority Indicator (PI)' and 'Dependency Matrix algorithm' that is responsible to minimize the power consumption of the resources without disturbing the data dependency present in the given problem. The proposed method also evenly distributes the allocated hardware functional units during the final scheduling. The comparison of the proposed approach with a recent approach in terms of exploration runtime and quality of final solution (measured using proposed 'Effective Cost Metric (ECM)') indicated an average improvement of 4.27% in the quality of final solution and reduction of 62.52% in exploration runtime.

Published in:

Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on

Date of Conference:

8-11 May 2011