By Topic

New processor array architecture for scalable radix 8 montgomery modular multiplication algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ibrahim, A. ; Dept. of Micro Electron., Electron. Res. Inst., Cairo, Egypt ; Gebali, F. ; Elsimary, H. ; Nassar, A.

This paper presents a new processor array architecture for scalable radix 8 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architectures extracted by G.Todorov. Moreover, the multi plier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance in terms of area, speed, and power consumption-than the previous radix 8 architecture extracted by G.Todorov.

Published in:

Electrical and Computer Engineering (CCECE), 2011 24th Canadian Conference on

Date of Conference:

8-11 May 2011