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A 4 GHz Continuous-Time \Delta \Sigma ADC With 70 dB DR and - 74 dBFS THD in 125 MHz BW

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4 Author(s)
Bolatkale, M. ; NXP Semicond., Eindhoven, Netherlands ; Breems, L.J. ; Rutten, R. ; Makinwa, K.A.A.

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm2 including the modulator, clock circuitry and decimation filter.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 12 )

Date of Publication:

Dec. 2011

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