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We investigated the variability impact of line edge roughness (LER) on standard inversion-mode (IM) and junctionless FinFETs (JL-FinFET) designed for the 2009 ITRS high-performance logic 32-, 21-, and 15-nm nodes using technology computer-aided design simulations. Fluctuations in threshold voltage, drive current, leakage current, subthreshold swing, and drain-induced barrier lowering were found to be significantly worse in junctionless devices compared to IM devices at root-mean-square LER amplitudes up to 1 nm. We invoke a simple physical argument to explain these findings based on the operating principles of IM and junctionless devices and the specific means by which LER affects both device architectures. Our findings show that JL-FinFETs are inherently more sensitive to variability than standard IM devices and will pose significant challenges as a feasible post-CMOS technology.