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The pursuit of higher performance has driven the bus based architecture toward network-on-chip (NoC). Meanwhile the three dimensional (3D) IC technology was suggested as a promising approach to reduce the wire length since the chip size became larger and larger. Because of the trend of hundreds or even thousands of processor cores integrated on one chip, it trigged a quest for the amalgamation of these two technologies above. As a result, 3D NoC emerged as a potent solution. In this paper, a hybrid hierarchical architecture for 3D multi-cluster NoC is proposed with the goal of optimizing the whole system performance. Each cluster is built based on hierarchical buses while global connections among clusters are formed with mesh topologies. The memory system is also divided into several layers and managed hierarchically. Both architectures and memory systems are discussed in detail and an analytical comparison of the average distance decreasing in the proposed architecture versus a standard NoC is presented. Experimental results indicate that the proposed architecture can improve the performance sharply. For writing operations, it can save 54.7% execution time in the best condition. While for reading operations, this value can reach 63.6%. And in a real communication-intensive application, 42.7% time savings have been observed compared to the conventional NoC.
Date of Conference: 3-5 Aug. 2011