STT-RAM Cell Optimization Considering MTJ and CMOS Variations

Spin-transfer torque random access memory (STT-RAM) becomes a promising technology for future computing systems for its fast access time, high density, nonvolatility, and small write current. However, like all the other nanotechnologies, STT-RAM suffers from process variations and environment fluctuations, which significantly affect the performance and stability of magnetic tunneling junction (MTJ) devices. In this study, we combine magnetic and circuit simulations to quantitatively analyze the impacts of MTJ and CMOS variations on the STT-RAM designs. Both bit-to-bit and cycle-by-cycle variations are considered. A robust STT-RAM design flow is also proposed.