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Summary form only given. As we continue scaling towards 14 nm and beyond, reliability is becoming an integral part of the complete technology offering. Building in reliability is critical to the success of future scaling. As we marched towards the sub 100 nm technologies material changes have been necessary to meet the power, performance and reliability requirements. In sub 45 nm regime SiOx based dielectrics have been replaced by HK MG leading to new degradation mechanisms such as PBTI and also changed the understanding of existing mechanisms such as TDDB. Similar challenges exist for backend and middle-of-line reliability where scaling presents challenges for RC delay as well as metal and dielectric reliability. Process solutions for improved electromigration reliability like alloy seed enhancement and metal capping degrade the resistance of interconnect and impact the dielectric reliability. Double patterning approaches also bring with them additional impacts to dielectric spacing and metal reliability. As we move beyond 20 nm new architecture and materials such as FINFETs and III–V channels will appear. It is critical to leverage our learning from past and develop understanding and solutions for the upcoming challenges.