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In the first part of this paper, we have discussed our proposed scheme to realize delayed least mean square (DLMS) adaptive filter with low-adaptation delay to have better convergence performance and to maintain small critical path to support high input sampling rate. Besides, we have proposed a novel multiplication cell for efficient implementation of error estimation block and weight update block of the adaptive filter. In this part of the paper, we have presented the complete architecture of the proposed DLMS adaptive filter with optimized the number of pipeline latches across the time-consuming combinational blocks of the structure to achieve low-adaptation delay and less critical path. From the synthesis results we find that the existing direct-form structure of  involves nearly 83% more area-delay product (ADP) and nearly 170% more energy-delay product (EDP) than the proposed one, in average, for filter orders N = 8, 16 and 32. The best of the existing systolic structures , similarly, involves nearly 21% more ADP and nearly 18% higher EDP than the proposed one for the same filter orders.
Date of Conference: 7-10 Aug. 2011