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A dual-mode power amplifier is designed in 65nm CMOS technology to have high efficiency at power back-off. It consists of two branches, one branch is a two-stage class A amplifier and the other is a three-stage class C amplifier. This amplifier has two different modes of operation at power back-off and at peak power. The main design issues for having high efficiency at output power back-off are discussed and considered in the design. Simulation results show a power-added efficiency of more than 13% at 5 dB output power range and 14.2dBm saturated output power.