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Systematic design of multi-bit continuous-time delta-sigma modulators using two-step quantizer

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3 Author(s)
Sakkarapani Balagopal ; Electr. & Comput. Eng. Dept., Boise State Univ., Boise, ID, USA ; Rajaram Mohan Roy Koppula ; Vishal Saxena

A 500 MS/s, wideband 4th order continuous-time delta sigma modulator (CT-ΣΔM) using a two-step 5-bit quantizer, consisting of only 10 comparators, is proposed and presented using 0.18μm CMOS technology. A proposed modulator takes advantage of the high resolution two step quantization technique and an excess loop compensation of more than one cycle to achieve a low-power, high dynamic range with a wide conversion bandwidth. A robust systematic design method is used to determine the loop filter coefficients by considering the non-ideal opamps effects including the finite gain and the presence of multiple internal poles and zeros. The proposed CT-ΣΔM achieves a dynamic range of 75.83 dB, peak SNR of 75.1 dB with 25 MHz bandwidth (OSR = 10) while consuming only 27.5 mW from the 1.8 V supply. The relevant design trade offs have been investigated and presented with simulation results.

Published in:

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

Date of Conference:

7-10 Aug. 2011