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3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption

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5 Author(s)
Inoue, K. ; Fac. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan ; Hashiguchi, S. ; Ueno, S. ; Fukumoto, N.
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This paper introduces our research status focusing on 3D-implemented microprocessors. 3D-IC is one of the most interesting techniques to achieve high-performance, low-power VLSI systems. Stacking multiple dies makes it possible to implement microprocessor cores and large caches (or DRAM) into the same chip. Although this kind of integration has a great potential to bring a breakthrough in computer systems, its efficiency strongly depends on the characteristics of target application programs. Unfortunately, applying die stacking implementation causes performance degradation for some programs. To tackle this issue, we introduce a novel cache architecture consisting of a small but fast SRAM and a stacked large DRAM. The cache attempts to adapt to varying behavior of application programs in order to compensate for the negative impact of the die stacking approach.

Published in:

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Date of Conference:

7-10 Aug. 2011