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Three-dimensional (3-D) memory stacking can resolve memory bandwidth challenges in chip multi-cores by stacking multiple dies of cache memory via inter-die wires between the stacked memories and multiprocessors. However, high power density (i.e., power dissipation per unit volume) due to the high integration incurs temperature-related problems in reliability, power consumption, performance, and system cooling cost. In this paper, we propose a solution to maximize the instruction throughput for temperature-constrained multi-core systems with 3-D stacked cache memory. The proposed method combines cache data allocation (including power gating of cache memory banks) and voltage/frequency scaling of cores in a temperature-aware manner. Experimental results show that the proposed method offers performance improvement in terms of instructions per second (IPS) compared with existing methods that only perform either cache data allocation or voltage/frequency scaling.
Date of Conference: 7-10 Aug. 2011