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This paper concerns a low-power and small silicon area of a successive divider-line Analog-to-Digital Converter (SDL ADC) which is dedicated to digitally controlled Switched Mode Power Supply (SMPS) in implantable devices. The proposed ADC consists of a resistor network based on diode connected transistor used to replace the delay-line of the windowed delay-line ADC in order to reduce its power consumption and silicon area and to enhance its characteristics. To compensate process and temperature variations, a digital calibration technique is used to meet the specified static and dynamic output voltage regulations and avoid variations of the regulated SMPS output voltage. The proposed ADC is implemented in AMS 0.35 μm CMOS process. Simulation results show a current consumption as low as 1.5μA/MHz and conversion time less than 10 ns. The proposed circuit can be a solution for high switching frequency, which results on faster regulation of SMPS output voltage.