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A novel “ divide and conquer ” testing technique for memristor based lookup table

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4 Author(s)
Veeresh A. Hongal ; Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO, USA ; Raghavendra Kotikalapudi ; Yong-Bin Kim ; Minsu Choi

The recently proposed nanoscale asynchronous crossbar architecture based on memristor-based look up table (MLUT) combines the advantages of memristor technology and asynchronous design for viable nanoscale computing. In spite of having numerous merits over the clocked counterparts and previous asynchronous designs, it is bound to have inevitable defects due to nondeterministic nanoscale assembly. In order to assess the reliability of MLUT, there is a need to develop efficient testing techniques. Typical approach so far has been to test every crosspoint on each crossbar MLUT exhaustively; this is not only tedious but is also prohibitively time consuming for designs involving large number of MLUTs. This paper introduces a novel testing scheme based on “Divide and Conquer” approach to efficiently locate the defective memristors in a MLUT. The proposed testing scheme leverages upon a special current additive property of the memristor based multiplexer. It performs binary isolation of regions, reducing the search space by half whenever applicable. Numerical simulations clearly demonstrate that the approach is generic, deterministic, and scalable.

Published in:

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

Date of Conference:

7-10 Aug. 2011