By Topic

A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jonghong Kim ; Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Junhee Cho ; Wonyong Sung

NAND Flash memory controllers need to equip strong and high speed error correction blocks as the cell size scales down and multi-level cell technology is employed. We have developed an LDPC (low-density parity-check) decoder for NAND Flash memory error correction, and implemented it using a layered min-sum decoding architecture. A shortened (69615, 66897) regular EG-LDPC code that has the code rate of 96% is used, which has a good minimum distance and quasi-cyclic structure. In order to increase the decoding throughput and reduce the chip area, the word-length reduction of variable-to-check messages, compression of the check-to-variable information, and pipelined parallel architecture are employed. Furthermore, fixed-point arithmetic optimization of node update processing units is also conducted to mitigate the quantization error, thereby enhances the error performance of the decoder. The synthesis and simulation results show that the SRAM area storing check-to-variable messages is much reduced, which leads to 38% saving in hardware area compared to the non-optimized serial architecture, and the design also exhibits a good error performance that is close to that of the floating-point implementation. The decoder can achieve the maximum decoding throughput of 6.24Gb/s and occupies the chip area of 48m m2 with 0.13um CMOS process.

Published in:

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Date of Conference:

7-10 Aug. 2011