By Topic

Energy minimization of 3D cache-stacked processor based on thin-film thermoelectric coolers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Soojung Rho ; Dept. of Electr. Eng., KAIST, Daejeon, South Korea ; Kyungsu Kang ; Chong-Min Kyung

In this paper, we explore the energy optimization of the processor with 3D stacked cache memory based on thin-film thermoelectric coolers (TFTEC). 3D integrated circuit is suitable for applications requiring small size, high performance and memory capacity. However, 3D integration incurs high power density owing to high temperature and high leakage power. TFTEC as active cooler can be used to deal with high temperature and high leakage energy consumption and eventually to reduce overall energy consumption. Experimental results show that 3D processor with TFTEC achieves a reduction of total energy consumption of both processor and TFTEC by up to 20% compared with processor without TFTEC under a given task's deadline and temperature constraints.

Published in:

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Date of Conference:

7-10 Aug. 2011