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Squeezing maximizing performance out of 3D cache-stacked multicore architectures

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3 Author(s)
Khan, A. ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Kyungsu Kang ; Chong-Min Kyung

3D integration is one of the most promising options to fulfill the demands of high performance and large cache by integrating multiple processor cores and 3D stacked cache. There are however temperature problems in 3D integration. This paper presents a method for performance maximization of a 3D cache-stacked multicore system keeping the temperature under a given limit while by assigning the clock frequencies and number of cache banks to each core according to the requirement. We have done experiments on multiple benchmark programs and have found a peak 32% and an average 29.8% improvement in performance as compared to the base case which assigns the same frequency and the same number of banks to each core.

Published in:

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Date of Conference:

7-10 Aug. 2011