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Design of a CMOS track-and-hold amplifier for a 6-bit 1-GS/s interpolating flash ADC

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4 Author(s)
Geoghegan, K.B. ; Dept. of Electr. & Comput. Eng., Naval Postgrad. Sch., Monterey, CA, USA ; Heedley, P.L. ; Matthews, T.W. ; Michael, S.

The design of a CMOS track-and-hold amplifier (THA) for a 6-bit 1-GS/s interpolating flash ADC is presented. Since the goal of the overall project was to determine the performance of a new ADC calibration architecture, the THA was prohibited from being the limiting factor in the performance of the ADC; consequently the THA was required to have at least 56dB of signal-to-noise and distortion ratio (SNDR) at the Nyquist frequency. The THA architecture, design methodology, and supporting simulation results will be presented.

Published in:

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Date of Conference:

7-10 Aug. 2011

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