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The practical implementation of a scalable video encoder requires for very high processing demands. In particular, the H.264/SVC is an emergent standard which combines distinct complex techniques in order to remove redundant data among consecutive layers, impacting in the global encoder complexity increasing. In order to evaluate that, this paper presents a detailed analysis of the required demands of a practical H.264/SVC video encoder. Considering these demands, it is proposed here an innovative approach, which uses flexible computational hardware modules in order to perform iteratively the SVC intra computational coding, for both the base layer and enhancement layers. The proposed solution was implemented in VHDL and compared with other conventional hardware approaches, confirming significant memory and used chip area savings. The aim of this proposal is to contribute to the research community with an innovative and practical solution for the development of scalable video encoders.