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Differential capacitance-to-digital converter utilizing time-domain manipulation of intermediate signals

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4 Author(s)
Hyunjoong Lee ; Electr. Eng., Seoul Nat. Univ., Seoul, South Korea ; Jong-Kwan Woo ; Suhwan Kim ; ManHo Kim

To achieve high-resolution in electrically noisy environments as well as low-power, we propose a differential capacitance-to-digital converter (CDC) that utilizes three-level time-domain manipulation of intermediate signals. The proposed CDC, designed in 0.35 μm digital CMOS technology and simulated with HSPICE, achieves a 9-bit resolution at the power supply of 3.3 V with the superimposition of 600 mVpp 2.5 kHz square-wave noise disturbance, consuming the average power of 158.3 μW/sample.

Published in:

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Date of Conference:

7-10 Aug. 2011

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