By Topic

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Hyun-Woo Lee ; Hynix Semiconductor Inc., Gyeonggi-do, Korea ; Ki-Han Kim ; Young-Kyoung Choi ; Ju-Hwan Sohn
more authors

A 512 Mbit consumer DDR2 SDRAM that uses self-dynamic voltage scaling (SDVS) and adaptive design techniques is introduced in this paper. With the increase in the significance of process variation, higher performance requirements reduce the allowable design margin in DRAM circuits. However, self-dynamic voltage scaling gives a greater timing margin in the circuitry by changing the internal supply voltage in response to the operating frequency and process skew. By changing the internal supply voltage, the life time of the chip increases by more than 23 times when the supply voltage is lowered by 300 mV. The proposed adaptive design techniques include an adaptive bandwidth delay-locked loop and an adaptive clock gating. The former improves the performance by obtaining a wider valid data window and the latter saves on dynamic power consumption in the clock distribution network. The SDVS method reduces the IDD3P by 9.3% and the adaptive clock gating saves 8.8% of the IDD3N when measured at 200 MHz, 25°C The studied consumer DDR2 SDRAM was fabricated using 44 nm standard DRAM process technology. It occupies a 17.7 mm2 die area and operates using a 1.8 V power supply.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:47 ,  Issue: 1 )