Close category search window
 

Highly efficient balanced CMOS linear power amplifier with load immunity

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Jeon, H. ; Georgia Electron. Design Center GEDC, Georgia Inst. of Technol., Atlanta, GA, USA ; Yoon, Y. ; Kim, H. ; Huang, Y.-Y.
more authors

A 1.95 GHz linear power amplifier (PA) in a standard 0.18 m CMOS process is presented. The PA achieves the load insensitivity characteristic up to 2.5:1 VSWR condition and dual-mode operation with a balanced topology. The area of the PA is 1.6 × 1 mm2. With a 3.4 V power supply, the PA provides 40.4 of peak power-added efficiency (PAE) and 35 of PAE at 26.4 dBm of linear output power.

Published in:
Electronics Letters  (Volume:47 ,  Issue: 19 )

Date of Publication: September 15 2011

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.